The present invention presents a “smart verify” technique whereby multi-state memories are programmed using a verify-results-based dynamic adjustment of the multi-states verify range for sequential-state-based verify implementations. This technique can increase multi-state write speed while maintaining reliable operation within sequentially verified, multi-state memory implementations. It does so by providing “intelligent” means to minimize the number of sequential verify operations for each program/verify/lockout step of the write sequence. In an exemplary embodiment of the write sequence for the multi-state memory during a program/verify cycle sequence of the selected storage elements, at the beginning of the process only the lowest state of the multi-state range to which the selected storage elements are being programmed is checked during the verify phase. Once the first storage state is reached by one or more of the selected elements, the next state in the sequence of multi-states is added to the verify process. This next state can either be added immediately upon the fastest elements reaching this preceding state in the sequence or after a delay of several program cycles. The adding of states to the set being checked in the verify phase continues through the rest of the set of multi-states in sequence, until the highest state has been added. Additionally, lower states can be removed from the verify set as all of the selected storage elements bound for these levels verify successfully to those target values and are locked out from further programming.

Title
Smart verify for multi-state memories
Application Number
10/314055
Publication Number
20040109362
Application Date
December 5, 2002
Publication Date
June 10, 2004
Inventor
Yupin Kawing Fong
Fremont
CA, US
Daniel C Guterman
Fremont
CA, US
Geoffrey S Gongwer
Los Altos
CA, US
Agent
Parsons Hsue & de Runtz
CA, US
IPC
G11C 29/00
View Original Source