20020084000-A1 is referenced by 2 patents.

A semiconductor structure including a semiconductor substrate, at least one first crystalline epitaxial layer on the substrate, the first layer having a surface which is planarized, and at least one second crystalline epitaxial layer on the at least one first layer. In another embodiment of the invention there is provided a semiconductor structure including a silicon substrate, and a GeSi graded region grown on the silicon substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing. In yet another embodiment of the invention there is provided a semiconductor structure including a semiconductor substrate, a first layer having a graded region grown on the substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing, the first layer having a surface which is planarized, and a second layer provided on the first layer. In still another embodiment of the invention there is provided a method of fabricating a semiconductor structure including providing a semiconductor substrate, providing at least one first crystalline epitaxial layer on the substrate, and planarizing the surface of the first layer.

Title
Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization
Application Number
10/022689
Publication Number
20020084000
Application Date
December 17, 2001
Publication Date
July 4, 2002
Inventor
Eugene A Fitzgerald
Windham
NH, US
Agent
Samuels Gauthier & Stevens
MA, US
IPC
H01L 29/12
H01L 29/04
H01L 31/36
C30B 01/00
H01L 21/20
H01L 29/30
H01L 21/36
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