548799 is referenced by 42 patents.

A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).

Title
Method of manufacturing semiconductor device with offset sidewall structure
Application Number
091116293
Publication Number
548799
Application Date
July 22, 2002
Publication Date
August 21, 2003
Inventor
Oda Hidekazu
Sayama Hirokazu
Ota Kazunobu
Assignee
Mitsubishi Electric Corporation
IPC
H01L 021/8238