1020060058959 is referenced by 7 patents.

PURPOSE: A testing circuit and a testing method for a semiconductor device and a semiconductor chip are provided to prevent decoding and modulating data of the chip, by cutting a test mode setting ROM and a test pad after testing the semiconductor device and using Manchester encoding signal synchronously with a dividing clock. CONSTITUTION: In a testing circuit of a semiconductor device, a pad is formed on a diced region of a semiconductor wafer. A memory unit(6) is formed on the diced region, and stores a program for executing a test mode. A control circuit(5) is formed on a chip region of the semiconductor wafer, and decodes a logic signal input from the pad and sets a test mode by the program stored in the memory unit.

Title
Testing circuit and testing method for semiconductor device and semiconductor chip, especially preventing decoding or modulation of data after production of semiconductor chip
Application Number
1020060058959
Publication Number
1020070089561
Application Date
June 28, 2006
Publication Date
August 31, 2007
Inventor
Suzuki Hideaki
Mouri Haruyuki
Nakajima Masao
Sugiyama Hidetoshi
Assignee
Fujitsu
IPC
G11C 29/00