An address buffering and decoding architecture for a multiple bank (or N bank) simultaneous operation flash memory is described. For the duration of a read operation at one bank of the N banks, a write operation can only be performed on any one of the other N-1 banks. For the duration of a write operation at one bank of the N banks, a read operation can only be performed on any one of the other N- 1 banks. The address buffering and decoding architecture includes a control logic circuit (218), an address selection circuit located at each of the N banks, and address buffer circuitry (220). The control logic circuit (218) is used to generate N read select signals to select one bank of the N banks for a read operation and N write select signals to selection another bank of the N banks for a write operation. Each address select circuit is configured to receive from the control logic circuit (218) a respective one of the N read select signals and a respective one of the N write select signals. The address buffer circuitry (220) is used to simultaneously provide a write address and a read address in order to access core memory cells. Respective first portions of the write and read addresses are provided to the control logic circuit (218) to generate the respective N read select signals and N write select signals. Respective second portions of the write and read addresses are provided to the respective address selection circuit.

Title
Multiple bank simultaneous operation for a flash memory
Application Number
1020027012128
Publication Number
1020030014368
Application Date
September 14, 2002
Publication Date
February 17, 2003
Inventor
Cleveland Lee Edward
Nguyen Kendra
Akaogi Takao
Assignee
Spansion
IPC
G11C 16/08