1020000036733 is referenced by 9 patents.
PURPOSE: A method for planarizing an interlayer dielectric of a semiconductor device is provided to improve a step coverage and to easily perform a subsequent process, by filling an interlayer dielectric between ultra-fine patterns without a void and by performing a planarization process. CONSTITUTION: A plurality of conductive layer patterns(22) are formed on a semiconductor substrate(21). The first passivation layer(23) is formed on the conductive layer pattern. A wet-etch process is performed to remove impurities on the first passivation layer. A plasma treatment is performed regarding the surface of the first passivation layer to improve adhesion and planarization of the subsequent interlayer dielectric. A SiOxHy layer(25) is formed on the plasma-treated first passivation layer by using a low pressure chemical vapor deposition(LPCVD) method. The step of the SiOxHy layer is decreased in a mixture gas atmosphere using reaction source of H2O2, H2O, O2 and inert gas. The second passivation layer(26) is formed to prevent the SiOxHy layer from cracking by a subsequent heat treatment process. The SiOxHy layer is densified.