PROBLEM TO BE SOLVED: To improve the performance of an SDRAM by a method wherein the waiting time of a memory is reduced and the simultaneous operations in a same memory bank is made to be performed. SOLUTION: In a cache synchronous dynamic random access memory(SDRAM) device having a multibank architecture, the rows of data latched by a sensing amplifier 106A are stored in a row register 102A which can be addressed at random. A selective logic gate means inputs the rows of data to the gate of the row register selectively in accordance with the specific implemented synchronous memory operation of the cache SDRAM 100. Data inputted to the cache SDRAM 100 during the writing operation are received by a sensing amplifier and written in a memory bank array. Data which are outputted from the cache SDRAM during the reading command are read out of a register 102A only.

Title
Cache synchronous dram architecture enabling parallel dram operation
Application Number
09-280391
Publication Number
1998-208471
Application Date
October 14, 1997
Publication Date
August 7, 1998
Inventor
Steven William Tomashot
Jim Louis Rogers
Christopher Paul Miller
Assignee
Internatl Business Mach Corp &Lt IBM&Gt
IPC
G11C 11/401
G11C 11/407