PROBLEM TO BE SOLVED: To provide a clock generator using a CMOS counter with the same resolution as that obtained when the generator uses a high-speed ECL counter. SOLUTION: In order to generate a clock RATE in a prescribed period based on a reference clock CK in a period t1, the reference clock CK is inputted to a count clock generating circuit 3. When the clock CK is inputted to the circuit 3, the circuit 3 generates a count clock CCK in a period t2 which is (n) times as long as the period t1. A counter 5 counts the clock CCK and a comparator means compares the count value CO of the counter 5 with a period designating value N2 so as to secure a period N2.t2. On the other hand, the correction of N1.t1 is performed during the period N2.t2. Therefore, the clock RATE is generated in a period N2.t2+N1.t1.

Clock generator
Application Number
Publication Number
Application Date
July 10, 1996
Publication Date
January 27, 1998
Kuramoto Fumio
H03K 19/0175
G04F 10/04
H03K 05/00