PROBLEM TO BE SOLVED: To improve the use efficiency of a CPU and a CPU bus by making it possible to gain read access from the high-speed CPU bus to the low-speed IG bus without altering the protocol of the buses or occupying the CPU bus. SOLUTION: When the address of an address register 11 matches a prefetch indication address at the time of write operation, a control circuit 17 latches the address indicated with write data in an address part 13-1 of a prefetch buffer 13, makes a read for a prefetch to the 10 bus 30, and latches read data in a data part 13-1 of the prefetch buffer 13. When the address of the address register 11 matches the address of the address part 13-1 of the prefetch buffer 13 at the time of read operation, the control circuit 17 outputs the data of the data part 13-2 of the prefetch buffer 13 corresponding to the address to the CPU bus 20.

Bus bridge and computer system equipped with the bus bridge
Application Number
Publication Number
Application Date
February 28, 1996
Publication Date
September 5, 1997
Kawakami Takuya
G06F 05/06
G06F 13/36