PURPOSE: To improve the data processing performance and to speed up data transfer between a processor and a memory by composing a system of a bus interface circuit which decomposes and combines data to bus width. CONSTITUTION: The system consists of a system bus 6 which is connected to an input/output device 3 and a graphic display circuit 4 and the interface circuit 7 which decomposes and combines the data to the bus width by a holding means for temporary holding the data for the data transfer between a central processing unit 1 and a main storage device 2 and a switching means for switching the transfer direction of the data, and the optimum transfer synchronized with the operation of the central processing unit 1 is performed between the central processing unit 1 and main storage device 2. Consequently, the data transfer between the central processing unit 1 and main storage device 2 is speeded up and the data processor can be diverted without greatly altering the standard bus 6 to which the input/output device 3, graphic display circuit 4, etc., are connected.

Title
Data processor
Application Number
04-086611
Publication Number
1993-257882
Application Date
March 11, 1992
Publication Date
October 8, 1993
Inventor
Kawakami Takuya
Assignee
Nec
IPC
G06F 13/36
G06F 13/38