An apparatus and method are disclosed for switching the context of state elements of a very fast processor within a clock cycle when a cache miss occurs. To date, processors either stay idle or execute instructions out of order when they encounter cache misses. As the speed of processors become faster, the penalty for a cache miss is heavier. Having multiple copies 8, 10, 11 of state elements on the processor and coupling them to a multiplexer permits the processor to save the context of the current instructions and resume executing new instructions within one clock cycle. The invention is particularly useful for minimizing the average instruction cycle time for a pipelined processor 6 with a main memory access time exceeding 15 processor clock cycles. The number of processes who's states are duplicated may be large.