1158682-A2 is referenced by 10 patents and cites 8 patents.
A block-parallel decoding algorithm and corresponding decoder architecture utilizes a set of interconnected processing nodes configured in the form of a probability dependency graph. The probability dependency graph is characterized at least in part by a code used to encode blocks of bits or symbols, and the processing nodes implement a block-parallel decoding process for blocks of the bits or symbols to be decoded. The probability dependency graph may be, for example, a bipartite probability dependency graph which includes a set of N variable nodes and a set of T check nodes, with one of the N variable nodes being associated with each of N bits or symbols of a given block to be decoded.; A single iteration of the block-parallel decoding process produces within the variable nodes an updated estimate for every bit or symbol in the given block, and may produce within the variable nodes an a-posteriori probability associated with the decoded bit or symbol for a soft-decision decoder. As another example, the probability dependency graph may be in the form of a directional probability dependency graph with multiple levels of nodes including an initial level, at least one intermediate level and a final level, arranged such that calculations can be performed at each level without sequential intra-block dependencies. The outputs of the nodes of the final level give an estimate of the transmitted bits or symbols for the given block, and may provide an estimate of the corresponding a-posteriori probabilities for a soft-decision decoder.