1152327-A2 cites 4 patents.

A reconfigurable register array structure allows an agent to transmit data from a single channel or in bundled form from multiple channels. The structure makes economical use of valuable chip space by reducing the size of the overall register array system. A coalescing prestage (201) is used to collect data from single channels or from multiple channels and to multiplex the data, based on a priority scheme, to supply the data to a primary stage of first-in-first-out register arrays (210-213). The coalescing prestage (201) may include one or more first registers (210-213), a delay register (202-205), multiplexers (220-223) to select outputs of the first registers (210-213), and multiplexers (240) to select outputs of the delay register.; Alternatively, the coalescing prestage (201) may include one or more register array structures, each such structure having independent write ports, one for each channel. Data coalesced in the coalescing prestage (201) is provided to a primary stage. The primary stage may include one or more logical register arrays configured as one physical array. Separate write pointers may be used to ensure data from a particular channel is provided to the correct location in the physical array.

Title
Reconfigurable fifo interface to support multiple channels in bundled agent configurations
Application Number
EP20010303902 20010430
Publication Number
1152327 (A2)
Application Date
April 30, 2001
Publication Date
November 7, 2001
Inventor
Jones Jason
US
Sharma Debendra Das
US
Swanson Jeffrey C
US
Assignee
Hewlett Packard Co
US
IPC
G06F 05/06
G06F 05/06
G06F 13/38
G06F 05/06
G06F 13/38
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