0747816-A2 is referenced by 36 patents and cites 3 patents.

A method and system for enhanced performance multithread operation in a data processing system which includes a processor, a main memory store and at least two levels of cache memory. At least one instruction within an initial thread is executed. Thereafter, the state of the processor at a selected point within the first thread is stored, execution of the first thread is terminated and a second thread is selected for execution only in response to a level two or higher cache miss, thereby minimizing processor delays due to memory latency. The validity state of each thread is preferably maintained in order to minimize the likelihood of returning to a prior thread for execution before the cache miss has been corrected.; A least recently executed thread is preferably selected for execution in the event of a nonvalidity indication in association with all remaining threads, in anticipation of a change to the valid status of that thread prior to all other threads. A thread switch bit may also be utilized to selectively inhibit thread switching where execution of a particular thread is deemed necessary.

Title
Method and system for high performance multithread operation in a data processing system
Application Number
EP19960480079 19960531
Publication Number
0747816 (A2)
Application Date
May 31, 1996
Publication Date
December 11, 1996
Inventor
Rose James Allen
US
Mullins Timothy John
US
Kunkel Steven Raymond
US
Kossman Harold F
US
Johnson Ross Evan
US
Eickemeyer Richard James
US
Assignee
Ibm
US
IPC
G06F 09/46
G06F 12/08
G06F 09/46
G06F 09/38
G06F 12/08
G06F 09/48
G06F 09/38
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