0697653-A1 is referenced by 7 patents and cites 3 patents.

A processor system comprises, in addition to a plurality of processors, a thread managing circuit which includes a load status table containing a corresponding number of load status counters each holding the load status of the corresponding processor. Each of the processor can access all the load status counters to know the dynamic load status of all the processors and to control the parallelism by using the dynamic load status of all the processors.

Title
Processor system and method for controlling the same
Application Number
EP19950112618 19950810
Publication Number
0697653 (A1)
Application Date
August 10, 1995
Publication Date
February 21, 1996
Inventor
Torii Sunao C O Nec Corp
JP
Motomura Masato C O Nec Corp
JP
Assignee
Nippon Electric Co
JP
IPC
G06F 09/46
G06F 15/16
G06F 09/46
G06F 09/38
G06F 15/177
G06F 15/17
G06F 15/16
G06F 09/50
G06F 09/46
G06F 09/38
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