0606758-A1 is referenced by 122 patents and cites 7 patents.

A method for making a dynamic random access memory by silicon-on-insulator comprising the steps of: dividing a cell area and a peripheral area on a first silicon substrate (1) and recessing just the cell area where a memory device is formed; forming a first insulating layer (3) by isolation of electrical elements in order to divide an active region and a passive region; forming and patterning a first conductive layer (15) through a contact to which the active region and a capacitor are connected on the insulating layer to form a storage node; forming a dielectric layer of the capacitor on the storage node (6); forming and patterning a polysilicon layer on the dielectric layer to form a storage node; forming a second insulating layer (11) on the plate node and planarizing the insulating layer by thermal treatment; forming a third conductive layer (13) to a predetermined thickness on the planarized insulating layer; polishing and planarizing the third conductive layer by chemical-mechanical polishing technique using a second insulating layer as an etchstopper and bonding a second silicon substrate (15) on the planarized third conductive layer; planarizing a backside of the first substrate by a chemical-mechanical polishing technique and exposing the active region (11); and forming a switching element and a bit line.

Title
Soi transistor dram device and method of producing the same.
Application Number
EP19930310488 19931223
Publication Number
0606758 (A1)
Application Date
December 23, 1993
Publication Date
July 20, 1994
Inventor
Lee Kyungwook
KR
Ban Cheonsu
KR
Lee Yeseung
KR
Park Kyucharn
KR
Assignee
Samsung Electronics
KR
IPC
H01L 21/82
H01L 27/108
H01L 27/12
H01L 27/108
H01L 23/52
H01L 21/70
H01L 27/10
H01L 27/12
H01L 27/108
H01L 23/52
H01L 21/8242
H01L 27/10
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