0548866-A2 is referenced by 9 patents and cites 3 patents.

In collectively and electrically erase a plurality of memory cells, to set the threshold values of the memory cells constant, electrons are previously stored in the floating gates of the memory cells (M11-Mlm) (S1). The memory cells whose floating gates are accumulated with electrons are electrically erased and the threshold value of each erased memory cell is checked. The collective erasing of the memory cells is repeated until the threshold values of all the memory cells become equal to or below a first value (VEV) (S2-S9). When it is detected that the threshold values of the memory cells become equal to or below the first value (VEV), it is discriminated if those threshold values are equal to or above a second value (VTN(E)min) smaller than the first value (S10-S15).; When there is a memory cell whose threshold value is equal to or below a minimum value (VTN(E)min) allowable on the design base in the previous discrimination step, that memory cell is over-erased and the memory chip containing the memory cell is determined as a defect (S12).

Title
Non-volatile semiconductor memory device.
Application Number
EP19920121678 19921221
Publication Number
0548866 (A2)
Application Date
December 21, 1992
Publication Date
June 30, 1993
Inventor
Hashimoto Kiyokazu C O Nec Cor
JP
Assignee
Nippon Electric Co
JP
IPC
G11C 29/00
G11C 16/06
G11C 29/04
G11C 29/00
G11C 16/06
G11C 17/00
G11C 29/50
G11C 29/12
G11C 29/00
G11C 16/16
G11C 17/00
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