A parallel and pipelined computer processor having a plurality of arithmetic and logic units (ALUs) which process computer operations in parallel to speed up the operation of the computer. Operations issued during the branch delay period following conditional jump operations are conditioned on the outcomes of the condition evaluation of such conditional jump operations that have not yet gone through the instruction issue pipeline, by matching a field in the operation to path information generated by a branch control unit. Operations that succeed are allowed to proceed and the effects of unsuccessful operations are disabled. This allows look-ahead computation after a conditional branch which is particularly attractive for a VLIW processor having a large number of parallel functional units and allows useful work to be done in the branch delay periods.; Optionally, only such operations that affect the programmer-visible state of the computer are so conditioned, e.g., store operations to memory, program flow control operations and operations that raise exception conditions. The matching algorithm can be implemented such that an operation is enabled on a single path or on an arbitrary set of paths.