0473420-A2 is referenced by 26 patents and cites 2 patents.

An instruction memory apparatus for a data processing unit stores a sequence of instructions. At each instruction fetch cycle, two sequentially adjacent instructions are accessed. An instruction preprocessing unit, coupled to the internal instruction memory, combines the two sequentially adjacent instructions into a single long instruction word when the two instructions meet predefined criteria for being combined. The first of the two instructions is combined with a no-operation instruction to generate along instruction word when the predefined criteria are not met. In that case, the second instruction may be accessed again during the next instruction fetch cycle as the first of two adjacent instructions.

Virtual long instruction word memory architecture for digital signal processor.
Application Number
EP19910307890 19910828
Publication Number
0473420 (A2)
Application Date
August 28, 1991
Publication Date
March 4, 1992
Baji Toru
Haigh Stephen G
G06F 09/38
G06F 09/38
G06F 09/38
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