0369405-A2 cites 4 patents.

Disclosed is a bus driver having a composition in which at least two P channel MOS transistors (P1, P2) and at least two N channel MOS transistors (N1, N2) are employed and these are respectively connected in series. A data signal is inputted into a gate of one of the P channel MOS transistors (P1), an inverted input of an enable signal is inputted into a gate of the other of the P channel MOS transistors (P2), the enable signal is inputted into a gate of one of the N channel MOS transistors (N1) and the data signal is also inputted into a gate of the other of the N channel MOS transistors (N2). Further, an output signal is outputted from a connection point (Z) of the P channel MOS transistors (P2) and the N channel MOS transistors (N1).; Also disclosed is another composition of a bus driver in which an inverted signal of an enable signal is inputted into the other of the P channel MOS transistors through an inverter. Also disclosed is a clocked inverter for use in the bus driver.

Title
Bus driver integrated circuit and a clocked inverter for use therein.
Application Number
EP19890121077 19891114
Publication Number
0369405 (A2)
Application Date
November 14, 1989
Publication Date
May 23, 1990
Inventor
Omote Kazuyuki Shirahatanaka
Kudou Tsuneaki Hamacho
Tokumaru Takaeji Nakatacho
Assignee
Toshiba Micro Electronics
JP
Tokyo Shibaura Electric Co
JP
IPC
G06F 13/40
H04L 25/02
H03K 19/094
H03K 17/687
G06F 13/40
G06F 03/00
H04L 25/02
H03K 19/094
H03K 17/687
G06F 13/40
G06F 03/00
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