0349123-A2 is referenced by 2 patents and cites 2 patents.

Multi-processor systems are often implemented using a common system bus as the communication mechanism between CPU, memory, and I/O adapters. It is also common to include features on each CPU module, such as cache memory, that enhance the performance of the execution of instructions in the CPU. Many architectures require that the hardware employ a mechanism by which the data in the individual CPU cache memories is kept consistent with data in main memory and with data in other cache memories. One such method involves each CPU monitoring transactions on the system bus, and taking appropriate action when a transaction appears on the bus which would render data in the CPU's cache incoherent.; If the CPU uses queues to hold records of incoming transaction information until it can service them, the bus interface must guarantee that the queued items are processed by the cache in the correct order. If this is not done, certain types of shared data protocols fail to operate correctly. The present invention describes a method by which hardware can guarantee the serialization of transactions requiring service by the CPU cache. The serialization method described guarantees that shared memory protocols operate correctly.

Multi-processor computer system having shared memory, private cache memories, and invalidate queues having valid bits and flush bits for serializing transactions.
Application Number
EP19890305429 19890530
Publication Number
0349123 (A2)
Application Date
May 30, 1989
Publication Date
January 3, 1990
Durdan Hugh W
Uhler Michael G
Callander Michael A
Digital Equipment
G06F 12/08
G06F 15/16
G06F 12/08
G06F 15/177
G06F 15/16
G06F 12/08
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