0201020-A2 is referenced by 18 patents and cites 4 patents.

Multiprocessor system architecture where two processors at least are provided each with an autonomous bus and the two buses can be selectively connected each other to constitute a unique system bus and to enable the access to common memory resources connected to an autonomous bus by all the processors; the processor communication taking place through messages stored into "mailboxes" included into the common memory resource and the presence of message being evidented by notify/interruption signals generated by a logic unit to which each processor has access to modify and verify its status, using its autonomous bus, without interferring with the operations running on the other autonomous busses and without requiring access to common memory resources and polling operations for verifying the pending status of messages into "mailboxes".

Multiprocessor system architecture.
Application Number
EP19860105844 19860428
Publication Number
0201020 (A2)
Application Date
April 28, 1986
Publication Date
December 17, 1986
Franzosi Antonio
Fiacconi Claudio
Honeywell Inf Systems
G06F 15/16
G06F 15/16
G06F 13/00
G06F 15/177
G06F 15/167
G06F 15/16
G06F 13/00
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