A process for fabricating silicon-on-insulator structures on semiconductor wafers and planarizing the topology of the patterns formed from the silicon. The process provides for the formation of monocrystalline silicon islands (19, 21) electrically isolated by dielectric in substantially coplanar arrangement with surrounding dielectric. As described, substrate silicon regions (13, 14) are initially formed and capped, and thereafter used as masks to etch the silicon substrate (1) between the regions. During the oxidation which follows, the capped and effectively elevated silicon regions (13, 14) are electrically isolated from the substrate by lateral oxidation through the silicon walls exposed during the preceding etch step, thereby providing silicon islands (19, 21). The capped regions, however, remain substantially unaffected during the oxidation.; With the electrically isolated silicon islands (19, 21) in place, a silicon dioxide layer (24) and a planarizing polymer layer (28) are deposited over the wafer. Processing is concluded with a pair of etching operations, the first removing polymer (28) and silicon dioxide (24) at substantially identical rates, and the second removing silicon dioxide (24) and monocrystalline silicon at substantially identical rates.