0126184-A2 is referenced by 40 patents and cites 4 patents.

An integrated circuit and method including a protection circuit (70) for an input to a CMOS device formed on a substrate (12) of a given impurity type has a resistive region (20) of an opposite impurity type to the substrate (12) formed therein, the region (20) having input (46) and output (48) connections thereto. A well (22) of the opposite impurity concentration is also formed in the substrate (12), the well (22) being connected to an electrical ground with respect to a first supply voltage lead (54) to the CMOS device. The first supply voltage lead (54) is electrically isolated from the substrate (12). An area (24) of the given impurity type is formed in the well (22), the area (24) and the output (48) connection being electrically common with the CMOS device input.; Finally, a second supply voltage lead (60) is electrically connected to the substrate (12) for biasing the substrate to a second supply voltage level exceeding a first supply voltage level.

Title
Input protection circuit and bias method for scaled cmos devices.
Application Number
EP19830112699 19831216
Publication Number
0126184 (A2)
Application Date
December 16, 1983
Publication Date
November 28, 1984
Inventor
Meyer Charles S
US
Assignee
Motorola
US
IPC
H01L 27/02
H01L 27/06
H01L 27/02
H01L 29/66
H01L 27/06
H01L 27/02
H01L 29/78
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