0009617-A1 is referenced by 97 patents and cites 3 patents.

A superheterodyne receiver employs as a local oscillator a VCO (125) included in a PLL (115). Upon depression of a station selecting switch (200), a pulse is generated and counted by a trinary counter (311) and two decimal counters (313, 315). The count value in the trinary counter is determined to indicate the channel index. The count value in the two decimal counters is subjected to the first addition (320) of "2" and the sum thereof is indicated as channel number data, while the same is subjected to multiplication (321) by 3 and the product thereof is subjected to the second addition (323) of a numerical value corresponding to the lowest channel frequency, whereupon the sum thereof is added in the third addition (327) to the count value in the trinary counter and the sum thereof is set in the PLL, while the same is indicated as the receiving frequency.

Title
Circuit for controlling a receiving frequency and a channel display in a superheterodyne receiver.
Application Number
EP19790103177 19790828
Publication Number
0009617 (A1)
Application Date
August 28, 1979
Publication Date
April 16, 1980
Inventor
Sumi Yasuaki
Assignee
Tokyo Sanyo Electric Co
JP
Sanyo Electric Co
JP
IPC
H04B 01/26
H03J 01/04
H03J 05/00
H03J 07/18
H03J 05/00
H03J 01/00
H03J 07/28
H03J 05/02
H03J 01/00
View Original Source Download PDF