A bus bridge (400) between two buses includes two request queues: outbound (420) and inbound (430). Requests originating on the first bus (401) which target a destination on the second bus (402) are placed into the outbound queue (420). If the request can be deferred, decoding circuitry (415) within the bridge (400) issues a deferred response to the originating agent, indicating the request will be serviced later. Bus control circuitry (425 ) removes requests from the outbound queue (420) and executes them on the second bus (402). When bus control circuitry (425) receives a response from the destination agent in response to this execution, it either returns the response to the originating agent immediately or after passing it through the inbound queue (430). Both queues (420, 430) have associated data buffers (520, 530) for transferring data between the two buses (401, 402). Requests are handled similarly in the opposite direction, with the request originating on the second bus (402) for execution on the first bus (401).

Procede et appareil servant a maintenir la commande des transactions et a supporter les reponses differees dans un pont pour bus
Method and apparatus for maintaining transaction ordering and supporting deferred replies in a bus bridge
Publication Number
Application Date
May 16, 1995
Publication Date
November 30, 1995
Meredith Susan S
Gonzales Mark A
Bell Michael D
Intel Corporation
Intel Corporation
G06F 13/40
G06F 13/00
View Original Source