A receiver or an integrated circuit (IC) incorporated therein includes a fast Fourier transform (FFT)-based (or hybrid FFT-based) sliding window block level equalizer (BLE) for generating equalized samples. The BLE includes a noise power estimator, first and second channel estimators, an FFT-based chip level equalizer (CLEQ) and a channel monitor unit. The noise power estimator generates a noise power estimate based on two diverse sample data streams. The channel estimators generate respective channel estimates based on the sample data streams. The channel monitor unit generates a first channel monitor signal including truncated channel estimate vectors based on the channel estimates, and a second channel monitor signal which indicates an approximate rate of change of the truncated channel estimate vectors. The FFT-based CLEQ generates the equalized samples based on the noise power estimate, one-block samples of the first and second sample data streams, the channel estimates and the monitor signals.

Title
Advanced receiver with sliding window block linear equalizer
Application Number
200680004512
Publication Number
101385239
Application Date
February 7, 2006
Publication Date
March 11, 2009
Inventor
Pan Kyle Jung lin
Kaewell John David Jr
Becker Peter Edward
Reznik Alexander
Difazio Robert A
Lin Bin
Agent
Guo Wei
Assignee
Interdigital Tech
IPC
H03H 07/30|H04B 01/10|H04L 01/00|H04L 25/08